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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
The differential interface for data and clock control is specified as below.
CHP
CLP
CLK
0V
-120 mV
+120 mV
-120 mV
-120 mV
50%
+120 mV
50% 50%
-120 mV -120 mV
+120 mV
(DIFFERENTIAL
CLOCK SIGNAL)
SPSTU
SPHLD
STH
2.0 V
2.0 V
0.9 V
1 st
2 nd
DIFFERENTIAL DATA
Invalid Data
+120 mV +120 mV
-120 mV -120 mV
+120 mV +120 mV
-120 mV -120 mV
3 rd
NOTE: Max CLK Frequency - 85 MHz
Figure 4. Timing Specifications 1
Table 5. Timing Specification 1
Symbol
CHP
CLP
STU
HLD
Parameter
Clock (CLK) High Period
Clock (CLK) Low Period
(R.G.B.) Setup to falling or rising edge of CLK
(R.G.B.) Hold from falling or rising edge of CLK
Conditions
f = 85 MHz
f = 85 MHz
f = 85 MHz
IPI = 100 μ A, f = 85 MHz
Min
-
-
1.875
0.225
Typ.
5.7
5.8
-
-
Max
-
-
-
-
Unit
ns
ns
ns
ns
SPSTU STH rising to CLK falling
SPHLD STH falling to CLK falling
RT = 100 Ω , CT = 5.0 pF, f = 85 MHz
RT = 100 Ω , CT = 5.0 pF, f = 85 MHz
3.0
1.5
-
-
-
-
ns
ns
V DIFF N
V DIFF P
VIH
VIL
VCM
GND
VIH
OV
VIL
(V DIFF P) - (V DIFF N)
Figure 5. CLK and Data input Specification
Table 6. Timing Specification 1
V CM = +1.2 V
Symbol
V IH
V IL
V CM
I DL
Parameter
High Input Voltage
Low Input Voltage
Common Mode Input Voltage Range
Input Leakage Current
Conditions
V CM = +1.2 V (9)
(9)
V IH = +70 mV, V IL = -70 mV
DxxP, DxxN, CLKP, CLKN
Min
70
-
0.9
-10
Typ.
200
-200
1.2
-
Max
-
-70
1.4
10
Unit
mV
V
μ A
Notes:
9.
VCM = (VCLKP+VCLKN)/2 or VCM = (VDxxP+VDxxN)/2
The positive sign means that DxxP (or CLKP) is higher than ground DxxN (or CLKN)
The negative sign means that DxxP (or CLKP) is lower than ground DxxN (or CLKN)
34848
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
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